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VLSI

Design and Verification:

  • Developing verification testbench components for chip/module level using System Verilog, C/C++
  • Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
  • Defining and executing detailed verification plan from spec working with architects, designers, system engineers.
  • Writing tests, Debugging tests, automating regression scripts and regression environment.
  • Incorporating code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.


SERVICES:

IP VERIFICATION:

  • System Verilog, UVM, OVM
  • Constraint Randmode TB
  • Functional coverage, Assertions, Code Coverage
  • Perl, python, specman

SOC VERIFICATION:

  • C++/C/Assembly Based Verification
  • System Verilog, UVM, OVM
  • Gate Level Verification
  • System level Verification/ FPGA Verification
  • Coverage Driven

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